Questions are transcribed from NTA's official question paper. Diagrams are described in words; open the official PDF to see them. Every answer was solved twice independently and is shown only when both agree. Where they did not, we say so.
2 April 2026 Shift 1, Q37 · Q37 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
For the given circuit (shown in part (A)) the time dependent input voltage $v_{in}(t)$ and corresponding output $v_o(t)$ are shown in part (B) and part (C), respectively. Identify the components that are used in the circuit between points X and Y.
[Figure: (A) Circuit diagram showing $v_{in}$ connected to an ideal diode and Zener diode ($V_Z = 5V$) in parallel with a capacitor between points X and Y, with output $v_o(t)$. (B) Input voltage graph showing sinusoidal wave oscillating between +20V and -20V over time. (C) Output voltage graph showing clipped wave at +5V and -5V over time.]
(1) [Figure: Resistor in series with diode from X to Y (69112130)]
(2) [Figure: Two diodes in opposite orientation from X to Y (69112131)]
(3) [Figure: Resistor in series with Zener diode from X to Y (69112132)]
(4) [Figure: Two diodes facing each other from X to Y (69112133)]
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Answer under review. Our two independent solutions did not agree, so we are not showing an answer yet. Check it against NTA's final answer key.
Key idea: Zener Diode Voltage Clipping Circuit - Back-to-Back Configuration
If $X$ and $Y$ are the inputs, the given circuit works as __________.
[Figure: Logic circuit diagram showing two NAND gates with inputs X and Y, their outputs connected to a NOR gate, followed by another gate leading to Output]
(1) OR gate
(2) AND gate
(3) NAND gate
(4) NOR gate
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Answer: Option (2)
Key idea: Logic Gates - NAND and NOR gate combinations, De Morgan's Laws
First NAND gate with both inputs as $X$: Output₁ = $\overline{X \cdot X} = \bar{X}$
Second NAND gate with both inputs as $Y$: Output₂ = $\overline{Y \cdot Y} = \bar{Y}$
NOR gate combines these outputs: Output = $\overline{\bar{X} + \bar{Y}}$
Apply De Morgan's Law: $\overline{\bar{X} + \bar{Y}} = \overline{\bar{X}} \cdot \overline{\bar{Y}} = X \cdot Y$
The final output is $X \cdot Y$, which is an AND gate
Two 4 bits binary numbers, $A = 1101$ and $B = 1010$ are given in the inputs of a logic circuit shown in figure below. The output $(Y)$ will be:
[Figure: A logic circuit with inputs A and B going through NAND and NOR gates to produce output Y]
(1) $Y = 1101$
(2) $Y = 0010$
(3) $Y = 0111$
(4) $Y = 1000$
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Answer under review. Our two independent solutions did not agree, so we are not showing an answer yet. Check it against NTA's final answer key.
Key idea: Bit-wise NAND operation on binary numbers
4 April 2026 Shift 1, Q42 · Q42 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
Consider a circuit consisting of a capacitor (20 $\mu$F), resistor (100 $\Omega$) and two identical diodes as shown in figure. The resistance of diode under forward biasing condition is 10 $\Omega$. The time constant of the circuit is $\alpha \times 10^{-3}$ s. The value of $\alpha$ is
[Figure: Circuit diagram showing a voltage source V connected in series with a capacitor C = 20 $\mu$F at the top, then a resistor R = 100 $\Omega$ on the right side, and two identical diodes connected in parallel (one forward and one reverse) at the bottom]
(1) 2.2
(2) 2.0
(3) 2.1
(4) 2.4
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Answer: Option (1)
Key idea: RC Time Constant with Diodes
Identify that two diodes in parallel (one forward, one reverse biased) have effective resistance equal to forward-biased diode: $R_{diode} = 10\,\Omega$
Calculate total resistance in series with capacitor: $R_{total} = R + R_{diode} = 100 + 10 = 110\,\Omega$
Use time constant formula: $\tau = R_{total} \times C$
Convert to required form: $\tau = 2.2 \times 10^{-3}\,\text{s}$
Therefore, $\alpha = 2.2$
4 April 2026 Shift 2, Q45 · Q45 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
Given below are two statements: one is labelled as **Assertion A** and the other is labelled as **Reason R**
**Assertion A:** A diode under reverse-biased condition provides very small current which is nearly independent of voltage until a critical limit at which the current increases drastically.
**Reason R:** Below the critical voltage limit, only majority charge carriers flow which increases drastically above critical voltage.
choose the *correct* answer from the options given below
(1) Both A and R are true and R is the correct explanation of A
(2) Both A and R are true but R is NOT the correct explanation of A
(3) A is true but R is false
(4) A is false but R is true
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Answer: Option (3)
Key idea: Reverse bias characteristics of p-n junction diode and breakdown mechanisms
In reverse bias, a small reverse saturation current flows due to **minority carriers** (not majority carriers) drifting across the junction
This reverse current remains nearly constant with voltage because minority carrier concentration is relatively independent of applied voltage
The reverse bias widens the depletion region, blocking majority carriers from crossing the junction
At the critical breakdown voltage, current increases drastically due to avalanche breakdown (impact ionization) or Zener breakdown (quantum tunneling)
**Assertion A is TRUE**: Correctly describes reverse bias behavior with small constant current until breakdown
**Reason R is FALSE**: Incorrectly states majority carriers flow in reverse bias (actually minority carriers flow)
Since A is true but R is false, the answer is option (3)
4 April 2026 Shift 2, Q46 · Q46 · Numerical · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
A diode has Zener voltage of 10 V and maximum power dissipation of 0.5 W, then the minimum resistance to be used in series with this diode for safety when it is connected to a 25 V power supply is _______ $\Omega$.
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Answer: 300
Key idea: Zener Diode Power Dissipation and Series Resistance Calculation
Find maximum Zener current: $I_{Z(max)} = \frac{P_{max}}{V_Z} = \frac{0.5}{10} = 0.05$ A
Calculate voltage across series resistance: $V_R = V_S - V_Z = 25 - 10 = 15$ V
Apply Ohm's law for minimum resistance: $R_{min} = \frac{V_R}{I_{Z(max)}} = \frac{15}{0.05} = 300$ Ω
Verify: Power dissipated = $V_Z \times I_{Z(max)} = 10 \times 0.05 = 0.5$ W (at maximum rating)
For the given logic circuit, which of the following inputs combination will make both LED−1 and LED−2 to glow?
[Figure: Logic circuit with inputs A, B, C showing NAND gates, NOT gates connected to two LEDs (LED-1 and LED-2) with resistors]
(1) $A = 0, B = 1, C = 1$
(2) $A = 1, B = 0, C = 0$
(3) $A = 1, B = 0, C = 1$
(4) $A = 1, B = 1, C = 0$
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Answer under review. Our two independent solutions did not agree, so we are not showing an answer yet. Check it against NTA's final answer key.
Key idea: Logic Gates - NAND and NOT gate operations, LED circuit analysis
5 April 2026 Shift 2, Q45 · Q45 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
In a semiconductor p-n diode, the doping concentrations on p-side and n-side are $10^{15}$ atoms/cm$^3$ and $10^{18}$ atoms/cm$^3$, respectively. Which one of the following statements is true?
(1) Widths of depletion region on either side of the interface are equal
(2) The depletion region width is more on p-side compared to that in n-side
(3) The depletion region width is more on n-side compared to that in p-side
(4) No depletion region forms because of unequal doping concentrations on p and n-sides
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Answer: Option (2)
Key idea: Depletion region width in p-n junction with unequal doping
The depletion region is much wider on the lightly doped p-side
6 April 2026 Shift 2, Q43 · Q43 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Medium
Refer to the logic circuit given below. For two inputs $(A=1, B=1)$ and $(A=0, B=1)$, output (Y) will be _________.
[Figure: Logic circuit with inputs A and B passing through NAND and NOR gates, producing output Y]
(1) 1, 0 respectively
(2) 0, 1 respectively
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Answer: Option (2)
Key idea: Logic Gates - NAND and NOR gate operations
Identify the logic gates in the circuit: NAND and NOR gates with inputs A and B
Determine output Y based on circuit configuration: Y follows NAND operation giving outputs $(0, 1)$ for the two input cases
Match with options: Output is $0$ for $(A=1,B=1)$ and $1$ for $(A=0,B=1)$ → Option (2)
8 April 2026 Shift 2, Q45 · Q45 · MCQ · Semiconductor Electronics: Materials, Devices and Simple Circuits · Easy
The output $Y$ for the given inputs $A$ and $B$ to the circuit is:
[Figure: Two timing diagrams showing inputs A and B as digital signals over time t(s) from 0 to 3. A logic circuit diagram showing inputs A and B connected through logic gates (AND gates followed by an OR gate) to produce output Y]
(1) [Figure: Timing diagram showing Y=1 from t=0 to t=1, then Y=0 from t=1 to t=3]
(2) [Figure: Timing diagram showing Y=1 from t=0 to t=2, then Y=0 from t=2 to t=3]
(3) [Figure: Timing diagram showing Y=0 from t=0 to t=1, Y=1 from t=1 to t=2, then Y=0 from t=2 to t=3]
(4) [Figure: Timing diagram showing Y=1 from t=0 to t=2, then Y=0 from t=2 to t=3]
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Answer under review. Our two independent solutions did not agree, so we are not showing an answer yet. Check it against NTA's final answer key.
Key idea: Digital Logic Gates - AND Gate Operation and Timing Diagrams
FAQs
Frequently asked questions
How many questions come from Semiconductors and Electronic Devices in JEE Main?
In the 9 shifts of JEE Main 2026 Session 2 we found 10 questions on it, about 1.1 per shift.
Where can I practise Semiconductors and Electronic Devices PYQs for free?
On this page, with solutions. For more, use NTA Abhyas and our free mock tests.
